1. Field
Exemplary embodiments of the present invention relate generally to a memory device.
2. Description of the Related Art
A memory cell of a memory device includes a transistor serving as a switch and a capacitor for storing data in the form of charges. “High” (logic 1) or “Low” (logic 0) logic data is determined depending on whether or not there is a charge in the capacitor of the memory cell, that is, whether a terminal voltage of the capacitor is high or low.
In principle, the retention of data does not consume power because the data is retained in such a way as to maintain charges accumulated in a capacitor. However, the data may be lost because the initial amount of charges stored in the capacitor is lost due to a leakage current attributable to the PN junction of a MOS transistor. To prevent such a loss, data within a memory cell is read before the data is lost, and the normal amount of charge is recharged based on the read information. Data is maintained only when such an operation is periodically repeated. Such a process for recharging cell charges is called a refresh operation.
A refresh operation is performed whenever a memory controller inputs a refresh command to a memory device. The memory controller inputs the refresh command to the memory device at a specific time interval by taking the data retention time of the memory device into consideration. The data retention time is indicative of the time during which the data of a memory cell can be retained without a refresh operation. Memory cells included in a memory device are designed to have a data retention time that is equal to or greater than a specific reference retention time. Thus, a time interval between consecutive refresh operations may be determined by taking the reference retention time of the device into consideration.
If some memory cells have a data retention time that is less than the device reference retention time due to some internal or external factor, there is an increasing possibility that these memory cells may lose their stored data. An internal factor that may cause a memory cell to have a lower retention time than the device reference retention time may be a cell defect. For example, when the cell capacitor of a memory cell has low capacitance or the cell transistor of a memory cell has high leakage current, these are internal factors that may influence the data retention time of the memory cell. Such a memory cell may also be referred to as a weak cell, and a word line to which the weak memory cell is coupled may also be referred to as a weak word line.
An external factor that may influence the data retention time of a memory cell of a memory device may include the temperature of the memory device and the voltage of an adjacent memory cell or a word line. For example, the data retention time of a memory cell is reduced due to a change in the temperature of a memory device. The amount of charges stored in a memory cell is influenced by the active and precharge operation of a word line adjacent to a word line to which the memory cell is coupled.
FIG. 1 is a diagram illustrating part of a cell array included in a memory device for explaining the influence of an external factor thereon. Reference “BL” denotes a bit line.
Referring to FIG. 1, three word lines WLK−1, WLK, and WLK+1 are disposed in parallel within the cell array. The word line WLK indicated by a reference “ATTACK_ACT” has a great number of active times, high active frequency, or a long active time, compared to the others. The word lines WLK−1 and WLK+1 are disposed adjacent to the word line WLK. Memory cells CELL_K−1, CELL_K, and CELL_K+1 are coupled to the word lines WLK−1, WLK, and WLK+1, respectively. The memory cells CELL_K−1, CELL_K, and CELL_K+1 include cell transistors TR_K−1, TR_K, and TR_K+1 and cell capacitors CAP_K−1, CAP_K, and CAP_K+1, respectively.
In FIG. 1, when the word line WLK is activated many times within a period of time, i.e., frequently, the voltage of the word line WLK is frequently toggled. When the word line WLK is activated for a long time the word line WLK maintains a high voltage for a long time. Coupling phenomena may be generated between the word line WLK and the word lines WLK−1 and WLK+1 and affect data stored in the memory cells CELL_K−1 and CELL_K+1 coupled to the word lines WLK−1 and WLK+1 which may negatively affect the data retention time of these cells.
Hence, further improvements are needed to reduce or overcome the aforementioned problems of prior art memory devices.